Xilinx Vivado Design Suite v2018.1 HLx Edition

Vivado® Design Suite HLx Editions include Partial Reconfiguration at no additional cost with the Vivado HL Design Edition and HL System Edition. In-warranty users can regenerate their licenses to gain access to this feature. Partial Reconfiguration is available for Vivado WebPACK™ edition at a reduced price.

The new HLx editions supply design teams with the tools and methodology needed to leverage C-based design and optimized reuse, IP sub-system reuse, integration automation and accelerated design closure. When coupled with the UltraFast™ High-Level Productivity Design Methodology Guide, this unique combination is proven to accelerate productivity by enabling designers to work at a high level of abstraction while facilitating design reuse.

Accelerating High Level Design
Software-defined IP Generation with Vivado High-Level Synthesis
Block-based IP Integration with Vivado IP Integrator
Model-based Design Integration with Model Composer and System Generator for DSP
Accelerating Verification
Vivado Logic Simulation
Integrated Mixed Language Simulator
Integrated & Standalone Programming and Debug Environments
Accelerate Verification by >100X with C, C++ or SystemC with Vivado HLS
Verification IP
Accelerating Implementation
4X Faster Implementation
20% Better Design Density
Up to 3-Speedgrade Performance Advantage for the low-end & mid-range and 35% Power Advantage in the high-end

Now available in the Vivado® Design Suite HLx Editions 2018.1 Release

Download Vivado Design Suite 2018.1 now, with support for:

Zynq UltraScale+™ RFSoC and Virtex UltraScale+ HBM devices
Increased productivity via ease of use improvements in IP flows and IP Integrator
New helper IPs and device support for Partial Reconfiguration
New capabilities and functions in Model Composer
Improved UltraScale+ Implementation: 5.5% higher Fmax, 1.6x faster compile times
Production devices introduced in this release
Zynq UltraScale+ MPSoC: XCZU11EG (-3), XCZU15EG (-3), XCZU17EG (-3), XCZU19EG (-3)
Kintex® UltraScale+: XCKU3P (-3), XCKU5P (-3), XCKU11P (-3), XCKU13P (-3), XCKU15P (-3)
Virtex UltraScale+: XCVU3P (-3), XCVU5P (-3), XCVU7P (-3), XCVU9P (-3)
Artix®-7 and Spartan®-7: XC7A25T (-2LE(0.9V)), XC7A12T (-2LE(0.9V)), XC7S100 (-1,-2), XC7S75 (-1,-2), XC7S25 (-1Q), XA7S25 (-1I,-2I,-1Q), XA7A25T (-1I, -2I, -1Q), XA7A12T (-1I,-2I,-1Q)
New Spartan-7 devices enabled: XC7S6, XC7S15, XA7S6 and XA7S15
New devices enabled in WebPACK
Artix-7: XC7A12T, XC7A25T
XA Artix-7: XA7A12T, XA7A25T
XA Spartan-7: XA7S25
Read about all of this and more in the Vivado 2018.1 release notes.

Design, Vivado, UltraScale, Edition, Suite, Partial, Reconfiguration, design, devices, Verification, Model, available, Accelerating, based, Level, System, Editions, reuse, Implementation, Vivado®, Design, Vivado, UltraScale, Edition, Suite, Partial, Reconfiguration, design, devices, available, Verification, Level, Accelerating, reuse, Model, System, based, Vivado®, Implementation, Editions